Conventionally, a semiconductor substrate is electrically connected to a circuit board by means of wire bonding. The wire bonding requires to ensure, on the outside of a chip, a space to which an end of a wire is connected. This increases the size of a package. Further, the wire bonding requires a long connection distance between the semiconductor substrate and the circuit board, thereby increasing inductance. For this reason, with the wire-bonding, it is difficult to increase a processing speed of a semiconductor device.
In order to solve these problems, Japanese Unexamined Patent Application Publication, Tokukai, No. 2006-54311 (published on Feb. 23, 2006; hereinafter, referred to as “Patent Document 1”) and Japanese Unexamined Patent Application Publication, Tokukaihei, No. 11-87391 (published on Mar. 30, 1999; hereinafter, referred to as “Patent Document 2”) propose a flip-chip bonding method. The flip-chip bonding method is such a bonding method that (i) a bump for bonding a semiconductor device to a circuit substrate is formed on a functional surface of the semiconductor substrate, (ii) the functional surface is set so as to face a surface of the circuit substrate, and (iii) the bump is bonded to an electrode on the circuit substrate.
FIG. 12 is a view illustrating a semiconductor device 71 described in Patent Document 1. The semiconductor device 71 includes: a semiconductor substrate 72; an Au bump 73 formed on an electrode 721 of the semiconductor substrate 72 and on a surface protection film 722 of the semiconductor substrate 72; a diffusion-prevention film 74 made of TiW; and a bonding film (solder) 75 formed on the diffusion-prevention film 74. TiW, which is material of the diffusion-prevention film 74, has a low diffusion coefficient for Au, so as to prevent diffusion between the Au bump 73 and Sn, which is material of the bonding film 75. Thus, it is maintained that the bonding film 75 is made of Sn purely.
One example of the flip-chip bonding method which is widely used is Au-solder bonding. The Au-solder bonding is a method for bonding together an Au bump formed on a semiconductor substrate and solder supplied on an electrode on a circuit board. This method utilizes Au—Sn metal bonding. Therefore, this method has high mounting reliability and is available in manufacturing fine-pitch products.
Also, such an arrangement is proposed that an Au bump is provided with a projection for the purpose of facilitating the process of flip-chip bonding. FIG. 13 is a cross-section view illustrating a process in which a semiconductor device 81 is mounted on a circuit board 6. FIG. 13 (a) illustrates a state where the semiconductor device 81 is not mounted on the circuit board 6 yet, and FIG. 13 (b) illustrates a state where the semiconductor device 81 has been mounted on the circuit board 6. The semiconductor device 81 includes: a semiconductor substrate 82; and an Au bump 83 which is provided on an electrode 821 on the semiconductor substrate 82. The Au bump 83 is provided with a projection 83a. An electrode 61 on the circuit board 6 is provided with solder 62.
As illustrated in the mounting structure in FIG. 13 (b), the projection 83a is inserted into the solder 62. This makes it possible to mount the semiconductor device 81 by applying a small weight.
In the arrangement illustrated in FIG. 13, however, the solder 62 is supplied only on the electrode 61 on the circuit board 6. Therefore, this arrangement cannot supply a sufficient amount of solder. As a semiconductor device has a higher density structure and a higher processing speed, the semiconductor device is required to have finer pitch between electrodes for flip-chip bonding, the electrodes being provided on a semiconductor substrate and on a circuit substrate. Having finer pitch between electrodes decreases the amount of solder which can be supplied. Therefore, it is difficult to enhance the mounting reliability in the arrangement illustrated in FIG. 13.
On the other hand, Patent Document 2 proposes an arrangement where solder is supplied, in advance, on an Au bump only.
FIG. 14 is a view illustrating a semiconductor device 91 described in Patent Document 2. The semiconductor device 91 includes: a semiconductor substrate 92 provided with an electrode 921; and an Au bump 93 provided on the electrode 921. Further, the Au bump 93 is provided with a projection 93a having a nose-shape. Also, the Au bump 93 is provided with solder 94 covering the projection 93a. However, Patent Document 2 does not disclose an arrangement where solder is supplied on the circuit substrate side in Therefore, in the arrangement illustrated in FIG. 14 also, it is impossible to ensure a sufficient amount of solder used for mounting a semiconductor device on a circuit board. That is, it is difficult to enhance the mounting reliability in the arrangement illustrated in FIG. 14, as well as in the arrangement illustrated in FIG. 13.
As such, the conventional arrangements described above have such a problem that sufficient mounting reliability cannot be attained.
Specifically, in the semiconductor device 71 described in Patent Document 1, the bonding film 75 is formed only on the top surface of the Au bump 73. Therefore, this arrangement cannot ensure a sufficient amount of solder, thereby decreasing the mounting reliability.
In the semiconductor device 81 illustrated in FIG. 13, as described above, the solder 62 is supplied only on the electrode 61 on the circuit board 6. Therefore, this arrangement cannot supply a sufficient amount of solder. That is, it is difficult to enhance the mounting reliability. Further, in the state illustrated in FIG. 13 (b), there is a case where the solder 62 reaches the electrode 821. If a high-temperature storage test is carried out with such a state, the solder 62 comes in an interface between the Au bump 83 and the electrode 821. This forms an intermetallic compound of Au and Sn, thereby causing a breakage in an early stage.
In the arrangement described in Patent Document 2, the solder 94 is directly supplied on the Au bump 93. This increases the amount of Au which diffuses in the solder 94, thereby leading to dissolution of the bump. Because the projection 93a on the Au bump 93 is thin, the mounting reliability will be significantly decreased if the projection 93a on the Au bump 93 is dissolved. Further, in this case, the solder has already reached the Au bump 93. This further increases the possibility of a breakage caused by the solder which has reached the electrode.
Patent Document 2 does not disclose such an arrangement that solder is supplied also on an electrode on a circuit board for the purpose of mounting a semiconductor device on the circuit board. That is, because the solder is supplied only on the Au bump 93, it is impossible to mount the semiconductor device 91 on the circuit board with a sufficient amount of solder. For this reason, it is impossible to enhance the mounting reliability in the arrangement described in Patent Document 2.
In the semiconductor device 81 illustrated in FIG. 13, the following arrangement is possible: The size of the Au bump 83 is increased so that the Au bump 83 touches the surface protection film 822 and covers the electrode 821 completely. This arrangement prevents the solder 62 from coming in the interface between the Au bump 83 and the electrode 821. However, in this arrangement, bonding pressure generated in the process of forming the Au bump 83 can cause a crack on the surface protection film 822.